1. Field of the Invention
This application relates to a liquid crystal display (LCD) device, and more particularly to a thin film transistor array substrate and method for fabricating the same.
2. Discussion of the Related Art
In general, the light transmittance of a liquid crystal with a dielectric anisotropy in LCD devices is controlled by an electric field in order to display an image. The LCD devices are usually fabricated by combining a color filter array substrate and a thin film transistor array substrate with a liquid crystal layer disposed between the two substrates.
Recently, LCD devices of several new modes are being developed in order to improve the narrow viewing angle of the related art LCD device. LCD devices with a wide viewing angle are classified into various modes including an in-plane switching (IPS) mode, an optically compensated birefringence (OCB) mode, a fringe field switching (FFS) mode, and other modes.
Among LCD devices with a wide viewing angle, the IPS mode LCD device allows a pixel electrode and a common electrode to be arranged on the same substrate so that a horizontal electric field is induced between the electrodes. As such, major axes of liquid crystal molecules are aligned in a horizontal direction with respect to the substrate. Accordingly, the IPS mode LCD device has a wider viewing angle than that of a TN (Twisted Nematic) mode LCD device of the related art.
FIG. 1 is a view showing a pixel structure in an IPS mode LCD device according to the related art. FIG. 2 is a cross-sectional view showing the pixel structure taken along a line I-I′ in FIG. 1.
As shown in FIGS. 1 and 2, a gate line 1 and a data line 5 cross each other so that a pixel region is defined. A thin film transistor TFT is used as a switching element and is disposed at an intersection of the gate and data lines 1 and 5.
On the pixel region, a first common line 3 opposite to the gate line 1 crosses the data line 5. First common electrodes 3a, which are extended from the first common line 3 and parallel to the data line 5, are formed at both sides of the pixel region.
The gate line 1 is configured to include a gate electrode 1a with a widened width. A first storage electrode 6 is disposed adjacent to the gate electrode 1a. The storage electrode 6 is formed in a single body with the first common electrodes 3a. 
Also, a second common line 13 electrically connected to the first common line 3 is formed over the first common line 3. Second common electrodes 13a are extended from the second common line 13 toward the pixel region. In addition, third common electrodes 13b partially overlapping the first common electrodes 3a are extended from the second common line 13.
The second common electrodes 13a are alternately disposed with pixel electrodes 7a in the pixel region. The pixel electrodes 7a are extended from a second storage electrode 7 overlapping the first storage electrode 6.
FIG. 2 is a cross-sectional view showing the pixel structure taken along a line I-I′ in a region of the data line 5 in FIG. 1. In FIG. 2, a gate insulation film 12 is formed on a lower substrate 10. The data line 5 is formed on the gate insulation film 12. The first common electrodes 3a arranged at both sides of the data line 5 are formed on the lower substrate 10. The third common electrodes 13b are formed on a protective (or passivation) film 19 and partially overlap the first common electrodes 3a. 
The color filter array substrate is configured to include a black matrix 21 which is opposite to the data line 5. The black matrix 21 is formed on an upper substrate 20. A red (R) color filter layer 25a and a green (G) color filter layer 25b are formed along both sides of the black matrix 21. Overcoat 29 is formed on red (R) color filter layer 25a and green (G) color filter layer 25b. 
Such an IPS mode LCD device in the related art forces the width L1 of the black matrix 21 to become larger (for example, at least 36 μm) in order to prevent light leakage caused by light that is generated in a backlight unit and that passes around the edges of the pixel region. More specifically, the black matrix 21 is formed to reach to an edge of the first common electrode 3a so as to intercept light passing between the data line 5 and the first common electrode 3a in a direction inclined by at least a constant angle with respect to a vertical line. As a result, an aperture ratio of the pixel region decreases. In addition, since the first common electrodes 3a are arranged at both sides of the data line 5, it is difficult for a thin film transistor array substrate of the related art to increase the aperture ratio of the pixel region.